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Espressif Systems /ESP32-S2 /PMS /PRO_DRAM0_2

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Interpret as PRO_DRAM0_2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PRO_DRAM0_RTCFAST_SPLTADDR 0 (PRO_DRAM0_RTCFAST_L_R)PRO_DRAM0_RTCFAST_L_R 0 (PRO_DRAM0_RTCFAST_L_W)PRO_DRAM0_RTCFAST_L_W 0 (PRO_DRAM0_RTCFAST_H_R)PRO_DRAM0_RTCFAST_H_R 0 (PRO_DRAM0_RTCFAST_H_W)PRO_DRAM0_RTCFAST_H_W

Description

DBUS permission control register 2.

Fields

PRO_DRAM0_RTCFAST_SPLTADDR

Configure the split address of RTC FAST for DBUS0 access.
PRO_DRAM0_RTCFAST_L_R

Setting to 1 grants DBUS0 permission to read RTC FAST low address region.
PRO_DRAM0_RTCFAST_L_W

Setting to 1 grants DBUS0 permission to write RTC FAST low address region.
PRO_DRAM0_RTCFAST_H_R

Setting to 1 grants DBUS0 permission to read RTC FAST high address region.
PRO_DRAM0_RTCFAST_H_W

Setting to 1 grants DBUS0 permission to write RTC FAST high address region.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd